1. Field of the Invention
This invention relates generally to microprocessor control of plural integrated circuits (I.C.""s). More particularly, the invention relates to communication of data and control signals from a microprocessor to two separate I.C.""s that have different command protocols using shared output lines from the microprocessor.
2. Background Information
Microprocessors typically control many different peripheral devices in any particular application. Each of a plurality of individual I.C.""s that are under the common control of a microprocessor typically may have a unique command protocol requiring its own unique set of communication lines from the microprocessor. For example, the particular command protocols for operating an HEF4894B shift register I.C. (manufactured by Philips Semiconductor) and an LC7574FE vacuum fluorescent display driver I.C. (manufactured by Sanyo) are not identical; yet both devices may be used as peripherals to a microprocessor or microcontroller within a particular climate control module in an automotive vehicle, for example. When both an HEF4894B I.C. and an LC7574FE I.C. are connected to the same controlling microprocessor that issues commands to the them, prior art systems required each I.C. to have its own unique set of control lines. Additional control lines add cost not only to the microprocessor itself, but also increases circuit board size and cost.
More specifically, an automotive vehicle climate control system may include a control bezel with both indicator LED""s and an alphanumeric display. It was desired to use an HEF4894B shift register I.C. to control the LED""s and an LC7574FE display driver I.C. to control a vacuum florescent display. While both the HEF4894B I.C. and the LC7574FE I.C. were on a common circuit board, the controlling microprocessor was on a different board. Consequently, the wiring between circuit boards (e.g., a ribbon cable) would have to contain separate sets of lines for the I.C.""s. However, because space was at a premium, it was difficult to physically package the necessary number of wires required for two unique sets of communication lines. Shared lines between the microprocessor and the peripheral I.C.""s could be used if the communication protocols were compatible. However, substitution of different I.C.""s using identical protocols or the design and fabrication of a new ASIC (Application Specific I.C.) to replace the HEF4894B and LC7574FE I.C.""s would not be cost-effective.
The present invention relates to a solution for enabling plural I.C.""s having different command protocols to be served by a single set of common control lines. A command protocol may, for example, define how serial data is clocked into an I.C. The inventive principles are useful in circuit applications where it is desired to use particular individual I.C.""s because they possess certain functional attributes or performance capabilities, while economizing on the number of control and data lines between the I.C.""s and a controlling microprocessor. It is to be appreciated however that certain general inventive principles may be practiced in various and other circuit applications where such considerations may not be present.
Principles of the present invention will be disclosed with reference to a specific example of a particular circuit application using the two particular I.C.""s mentioned above, namely an HEF4894B I.C. and an LC7574FE I.C. It is also to be appreciated that general inventive principles may be practiced in other circuit applications using other than these two particular I.C.""s or using more that two I.C.""s.
The invention is particularly advantageous in that it reduces the number of microprocessor pins required to control multiple device I.C.""s and it cuts down on corresponding circuit board traces. These advantages become even greater when the invention is used in a circuit where multiple I.C.""s having diverse command protocols are located on a common circuit board which is remote from a circuit board containing a microcontroller that issues operating commands to the I.C.""s via a control line and data via a data line. In the case of the HEF4894B I.C. and the LC7574FE I.C., both I.C.""s are served by a common clock line connected to clock inputs of the I.C.""s. While a single serial data line serves both I.C.""s, data is loaded into the LC7574FE I.C., not by a direct connection of its data input to the single serial data line, but instead through the HEF4894B I.C. A single latch/chip enable line serves both I.C.""s, being connected directly to a chip enable input of the LC7574FE I.C. for delivering a signal, referred to as a chip enable signal, that is suitable for its protocol. An interface circuit on the same board that contains the two I.C.""s, interfaces the latch/chip enable line to a strobe (STR) input of the HEF4894B I.C. to supply a strobe signal suitable for its command protocol. The interface circuit performs voltage inhibit, pulse generation, and voltage limiting functions to allow use of one control line to serve both the chip enable input of the LC7574FE and the STR input of the HEF4894B.
While specific nomenclature appearing on the respective manufacturer""s specification sheets for these two I.C.""s may differ, each shows an internal block diagram containing a shift register, a latch, and communication lines, sometimes called control lines, for controlling operation of each device, the control lines including a clock line, a serial data input line, and a chip enable line on the LC7574FE and a strobe line on the HEF4894B. The LC7574FE I.C. is a device whose protocol requires proper addressing of the I.C. before serial data can be loaded. The commercial designation of that protocol is a C2B protocol, and certain principles of the invention are applicable to I.C.""s that use that protocol, both in addressable or non-addressable form, even if they are not specifically an LC7574FE I.C.
One general aspect of the invention relates to an electronic circuit comprising: discrete first and second integrated circuits each having a respective command protocol diverse from that of the other; the first integrated circuit having a clock input, a strobe input, a data input, a shift register, and an output buffer; the second integrated circuit having a clock input, a chip enable input, a data input, and an address decoder; a clock signal source for supplying a Clock signal comprising clock pulses to the clock inputs of the integrated circuits via a clock line; a data signal source for supplying a Data signal comprising serial data to the data inputs of the integrated circuits via a data line; a chip enable line supplying a Chip enable signal directly to the chip enable input of the second integrated circuit, the Chip enable signal comprising pulses that have leading edges defining change from a first logic state to a second logic state and trailing edges defining change from the second logic state to the first logic state; the second integrated circuit""s command protocol allowing serial data at its data input to be clocked in by clock pulses at its clock input when the signal at its chip enable input is in the second logic state and a correct address was loaded into its address decoder prior to the Chip enable signal changing from the first logic state to the second logic state and disallowing serial data at its data input from being clocked in by clock pulses at its clock input either when a signal at its chip enable input is in the first logic state or when a correct address was not loaded into its address decoder prior to the chip enable signal changing from the first logic state to the second logic state; an interface circuit interfacing the chip enable line to the strobe input of the first integrated circuit and supplying to the strobe input of the first integrated circuit a Strobe signal that has a leading edge defining change from the first logic state to the second logic state and a trailing edge defining change from the second logic state to the first logic state; the first integrated circuit""s command protocol allowing serial data at its data input to be clocked in by clock pulses at its clock input, when the signal at its strobe input is in the first logic state, allowing data in its shift register to transfer to its output buffer when a signal at its strobe input is in the second logic state, and disallowing data transfer to the output buffer when the signal at its strobe input is in the first logic state thereby latching data at the outputs; and the interface circuit comprising an inhibiting property that in response to change in the Chip enable signal from the first logic state to the second logic state, inhibits change in the signal at the strobe input of the first integrated circuit, and in response to change in the Chip enable signal from the second logic state to the first logic state, initiates a Strobe signal pulse to change the signal being applied at the strobe input from the first logic state to the second logic state, and then after a predefined delay, to revert back to the first logic state.
Another general aspect of the invention relates to an electronic circuit comprising: discrete first and second integrated circuits each having a respective command protocol diverse from that of the other; the first integrated circuit having a clock input, a strobe input, a data input, and a shift register; the second integrated circuit having a clock input, a chip enable input, and a data input; a clock signal source for supplying a clock signal comprising clock pulses to the clock inputs of the integrated circuits; a data signal source for supplying a serial data signal to the data input of the first integrated circuit; a chip enable signal source for supplying to the chip enable input of the second integrated circuit a chip enable signal; an interface circuit interfacing the chip enable signal to the strobe input of the first integrated circuit for supplying to the strobe input a strobe signal derived from the chip enable signal; the shift register having a serial data output at which data that has been clocked through the shift register after entering at the first integrated circuit""s data input is serially output; a connection from the serial data output of the shift register to the data input of the second integrated circuit so that data from the data signal source is presented to the second integrated circuit only after having been clocked through the shift register of the first integrated circuit; and in which the first integrated circuit, the second integrated circuit, and the interface circuit are disposed on a common circuit board, the clock signal source, the data signal source, and the chip enable signal source are not disposed on that common circuit board, and a clock signal line connects the clock signal source to the common circuit board, a data signal line connects the data signal source to the common circuit board, and a chip enable signal line connects the chip enable signal source to the common circuit board.
Other general and more specific aspects of the inventive principles will been set forth in the ensuing description and claims.